For the improvement of functionality and performance, semiconductor devices such as semiconductor integrated circuits are now equipped with a plurality of metal wiring layers for their internal wiring (multilayered wiring). In addition, semiconductor devices employ increasing numbers of bonding pads for the input and output of signals in and out of the semiconductor device.
In conventional multilayered wiring techniques, the bonding pad is often formed using the uppermost metal wiring layer, together with all the underlying metal wiring layers. Specifically, the shape of the bonding pad is substantially the same for that defined by the uppermost metal wiring layer as for those defined by the underlying metal wiring layers. These bonding pads of the respective metal wiring layers are then connected to one another through via holes or the like, so as to attain the same potential.
Such a configuration has been conventionally adopted for the reasons described below. In an alternative configuration where the bonding pad is formed only in the uppermost layer, an attempt to make a contact between the bonding pad and the underlying metal wiring layers or semiconductor element using only the via holes causes the following problems. First, position registration of the via holes becomes difficult in the respective layers. Another problem is the poor reliability of the connection between the respective layers through the via holes.
These drawbacks are solved by the foregoing configuration in which the bonding pads of the respective metal wiring layers are connected to one another through via holes or the like, so as to attain the same potential across these layers. By thus connecting the via holes through the metal wiring layers, contacts between these layers can be made more easily and more reliably.
A drawback of this configuration, however, is the problem it causes when the semiconductor element is disposed below the bonding pad. Namely, the bonding pad or an interlayer insulating layer between the bonding pads may crack by the impact caused by a tester prober in wafer testing, or a bonding head of a wire bonder in a bonding process in assembling the chip into a package in a later process. The crack may cause shorting of, for example, the bonding pad and the metal wire for the semiconductor element below the bonding pad, in which case the intended functions of the semiconductor element may be lost.
In recent years, integration of semiconductor devices has been advancing for higher functionality, larger capacity and system integration of the device. This has resulted in a proportional increase in chip size. Meanwhile, it is of a primary concern to reduce a chip size to lower chip cost. Various methods are available for the reduction of a chip size. For example, the reduction may be achieved by way of reducing the processing scale or simplifying the circuit. One method changes the layout of the device so that the area of the bonding pad can be used efficiently.
One example of such a technique for efficiently utilizing the area of the bonding pad is a technique known as an area pad technique, in which the active area of the semiconductor element is positioned below the bonding pad. However, it has been difficult to apply this technique to conventional structures as exemplified above, due to the susceptibility of the conventional structure to shorting caused by cracking in the bonding pad or the interlayer insulating layer between the bonding pads.
In applying the area pad technique, one way to overcome this drawback is to provide a thin film of organic material, such as a polyimide film, below the bonding pad, so as to absorb the force of impact. However, this causes another drawback in that it additionally requires a material, a processing device, or a processing step for providing such an organic thin film, which is disadvantageous in terms of cost of the semiconductor device.
Accordingly, in order to use the area pad technique, there is a need for a method that prevents cracking in the bonding pad or the interlayer insulating layer between the bonding pads, without greatly increasing the cost of the device.
In this connection, Japanese Publication for Unexamined Patent Application No. 1538/1991 (Tokukaihei 3-1538; published Jan. 8, 1991) discloses a technique for preventing cracking in the multilayered wiring technique. FIG. 8(a) is a plan view of a bonding pad 120 in a semiconductor device 100 disclosed in this publication, and FIG. 8(b) is a cross sectional view of the semiconductor device 100.
In the semiconductor device 100, a polycide wire 103a and a polycide wiring layer 103b are formed, via an insulating layer 102, on a surface of a semiconductor substrate 101 that is realized, for example, by a P-type silicon substrate 101a and an N-type silicon substrate 101b. On the stack of these layers are formed Al wiring layers 104, 105, and 106 with intervening interlayer insulating layers 107, 108, and 109. Finally, a surface protective coating 110 is formed to coat these layers.
The Al wiring layers 104, 105, and 106 constitute a bonding pad 120. The surface protective coating 110 on the Al wiring layer 106 is partially removed to create an opening 110a. The surface of the Al wiring layer 106 exposed in the opening 110a makes up an interconnection face 120a of the bonding pad 120.
In the interlayer insulating layers 108 and 109 are embedded a plurality of conducting members 111 and 112, respectively. In the interlayer insulating layer 107 is embedded a conducting member 113. The conducting members 111 through 113 are provided to connect the Al wiring layer 106 and the wire 103a to each other. The Al wiring layer 105 is provided to connect the conducting members 112 and 111 to each other, and the Al wiring layer 104 is provided to connect the conducting members 111 and 113 to each other.
The conducting members 111 and 112 are disposed in a staggered fashion so that they do not overlap with each other in a stacked direction of the layers. With this construction, the underlying Al wiring layers 104 and 105 can serve as a stress buffering layer when stress is exerted in a bonding process or other processes on the conducting members 111 and 112, for which a hard material is generally used. In this way, damage to the insulating layer 102 or the interlayer insulating layer 107 can be prevented.
Another technique for preventing cracking in the multilayered wiring technique is disclosed, for example, in Japanese Publication for Unexamined Patent Application No. 64945/1998 (Tokukaihei 10-64945; published Mar. 6, 1998). FIG. 9 is a perspective view of a bonding pad 200 in a semiconductor device disclosed in this publication.
The bonding pad 200 is structured such that electrodes 201 and 203 are connected to each other via conducting members 206 and 207 that are embedded in interlayer insulating layers 204 and 205. The conducting members 206 and 207 are connected to each other via an electrode 202. The electrode 202 has an openings 202a through which the interlayer insulating layers 204 and 205 are connected. With this construction, the interlayer insulating layers between the electrodes 201 and 203 make up a pillar 208, by which the interlayer insulating layers 204 and 205 are prevented from being cracked by a force of impact in a bonding process.
Despite the foregoing construction, the technique disclosed in Tokukaihei 3-1538 still has a high probability of developing cracks. The following describes a mechanism by which a crack is generated in the bonding pad or interlayer insulating layer in the construction of this publication.
Generally, wiring layers such as the Al wiring layers 104, 105, and 106 are made of a relatively softer material than that of the interlayer insulating layers 107, 108, and 109. In this case, when the bonding pad 120 is realized by multilayered metal of a relatively large area as in FIG. 8(a) and FIG. 8(b), the force exerted on the Al wiring layer 106 by a tester prober in wafer testing or by a bonding head of a wire bonder in a bonding process compresses and deforms the Al wiring layers 105 and 104, owning to the fact that the Al wiring layers 105 and 104 below the Al wiring layer 106 is materially softer. The force that compresses and deforms the Al wiring layers 104 and 105 generates stress that concentrates on deformed portions of the Al wiring layers 104 and 105 and the corresponding portions of the interlayer insulating layers 108 and 109. Thus, the area around the portions of concentrated stress has a high probability of developing cracking.
In should be note that, in order to prevent reflection of light during the exposure in a photolithography process, the upper and lower surfaces of the wiring layer are sometimes coated with barrier metal coatings, which are made of a relatively hard material such as TiN. These barrier metal coatings are also susceptible to cracking when the stress concentrates in the described manner.
Further, in the techniques disclosed in the foregoing publications, the area of the bonding pad is occupied by a plurality of layers defining the bonding pad. Consequently, the area of bonding pad cannot be used efficiently.
Taking the construction of Tokukaihei 10-64945 shown in FIG. 9 for example, the electrode 202 is integral with the electrodes 201 and 203 and connects the conducting members 206 and 207 to each other. In this respect, the electrode 202 can be regarded as a member that makes electrical connections in the stacked direction of the layers.
Meanwhile, a multiplicity of elements is two-dimensionally disposed on a plane of the substrate 209. In order to connect these elements, the wires formed on the plane of the electrode 202 may be used. In this case, the construction of FIG. 9 requires that the wires be formed by bypassing the area of the electrode 202. This is disadvantageous, in terms of wire layout, in efficiently utilizing the area of the bonding pad.
The same problem arises in the construction of Tokukaihei 3-1538 shown in FIG. 8(a) and FIG. 8(b).